Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a NAND type flash memory array architecture 100 wherein the floating gate memory cells 102 of the memory array are logically arranged in an array of rows and columns. In a conventional NAND Flash architecture, “rows” refers to memory cells having commonly coupled control gates, while “columns” refers to memory cells coupled as a particular NAND string, for example. The memory cells 102 of the array are arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each. Memory cells of a string are connected together in series, source to drain, between a source line 114 and a data line 116, often referred to as a bit line. Each series string of memory cells is coupled to source line 114 by a source select gate such as 110 and to an individual bit line 116 by a drain select gate 104, for example. The source select gates, such as 110, are controlled by a source select gate control line SG(S) 112 coupled to their control gates. The drain select gates, such as 104, are controlled by a drain select gate control line SG(D) 106. The one or more strings of memory cells are also typically arranged in groups (e.g., blocks) in which the one or more strings coupled to multiple bit lines of a particular group are formed in a common p-well 140 formed in the substrate of the memory device. Due to this commonality of the p-well 140 between the one or more strings of memory cells, each p-well region near each of the memory cell strings has the same potential, such as 0V, or might be left floating, for example.
The memory array is accessed by a row decoder (not shown) activating a logical row of memory cells by selecting a particular access line, often referred to as a word line, such as WL7-WL0 1187-1180, for example. Each word line is coupled to the control gates of a row of memory cells. Bit lines BL1-BL4 1161-1164 can be driven high or low depending on the type of operation being performed on the array. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
Memory cells 102 can be configured as what are known in the art as Single Level Memory Cells (SLC) or Multilevel Memory Cells (MLC). SLC and MLC memory cells assign a data state (e.g., as represented by one or more bits) to a specific range of threshold voltages (Vt) stored on the memory cells. Single level memory cells (SLC) permit the storage of a single binary digit (e.g., bit) of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of Vt ranges assigned to the cell and the stability of the assigned Vt ranges during the lifetime operation of the memory cell. The number of Vt ranges (e.g., levels), used to represent a bit pattern comprised of N-bits is 2N, where N is an integer. For example, one bit may be represented by two levels, two bits by four levels, three bits by eight levels, etc. MLC memory cells may store even or odd numbers of bits on each memory cell.
An MLC (four-level, e.g., 2-bit) memory cell might be assigned a Vt that falls within one of four different Vt ranges of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. Typically, a dead space (which is sometimes referred to as a margin) of 200 mV to 400 mV is maintained between each Vt range to keep the ranges from overlapping. As an example, if the voltage stored on a memory cell is within the first of the four Vt ranges, the cell in this case is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second of the four Vt ranges, the cell in this case is storing a logical ‘10’ state. A voltage in the third Vt range of the four Vt ranges indicates that the cell in this case is storing a logical ‘00’ state. Finally, a Vt residing in the fourth Vt range indicates that a logical ‘01’ state is stored in the cell.
FIG. 2 shows a side view of a single string of memory cells formed in a p-well 240 such as string 112 shown in FIG. 1, for example. The p-well 240 is also shown formed in an n-type well or a silicon-on-insulator (SOI) substrate 242 which are both known to those skilled in the art. The control gates of each memory cell are shown coupled to the word lines 118 as shown in FIG. 1. A source select gate 210 and drain select gate 204 are also illustrated.
FIG. 3 shows a view angle of the four NAND strings of memory cells. The view angle is that of looking into the NAND strings from a source select gate 310 viewpoint. FIG. 3 is shown in a simplified form to focus on the p-well structures and does not show the memory cells 102 of the array. Each NAND string might be formed in independent p-wells such as P+ regions 3121-4, for example. Other devices, such as described with respect to the common p-well 140 of FIG. 1, might have all of the NAND strings, formed not in individual p-wells as 3121-4, but instead share a common p-well as indicated by the dashed line 342.
Memory cells are typically programmed using erase and programming cycles. For example, memory cells of a particular block of memory cells are first erased and then selectively programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the word lines in the block and applying an erase voltage to a semiconductor substrate on which the block of memory cells is formed, and thus to the channels of the memory cells, in order to remove charges which might be stored on the floating gates of the block of memory cells. This typically results in the Vt of memory cells to reside in the lowest Vt range (e.g., erased state), for example.
Programming typically involves applying one or more programming pulses to a selected word line and thus to the control gate of each memory cell coupled to the selected word line. Typical programming pulses start at or near 15V and tend to increase in magnitude during each programming pulse application. While the program voltage (e.g., programming pulse) is applied to the selected word line, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, resulting in a charge transfer from the channel to the floating gates of memory cells targeted for programming. More specifically, the floating gates are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a Vt typically greater than zero in a programmed state, for example. In addition, an inhibit voltage is typically applied to bit lines not coupled to a NAND string containing a memory cell that is targeted for programming.
Typically, alternating bit lines are enabled and/or inhibited during a write (e.g., programming) and/or a read operation performed on a selected row of memory cells. During a programming operation, an effect which is known as program disturb can occur. For example, during a programming operation, some memory cells coupled to the selected word line may reach their assigned threshold voltage before other memory cells coupled to the same word line reach their assigned threshold voltages. This condition is especially likely to occur in MLC memory. The continued application of programming pulses (such as to complete programming of one or more memory cells of a row) to a selected word line can cause these program disturb issues. This is because memory cells which have reached their intended programming levels and are inhibited from programming can still experience a shift in their threshold voltage due to the continued application of programming pulses to the selected word line, for example. In particular, this can significantly affect inhibited memory cells which are in an erased state. In addition, memory cells coupled to unselected word lines can also experience program disturb in response to their proximity to a selected word line, for example. Undesirable leakage currents can also occur during a programming operation such as from the channel region of an unselected NAND string to the substrate and/or its associated bitline. These leakage currents can also contribute to program disturb effects.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for a way to manage substrate well biasing in a memory device in order to mitigate the effects of program disturb in flash memory devices.